1. Field of the Invention
The present invention relates to a hitless switching system of an ATM switch, and more particularly to a hitless switching system of an ATM switch which has a discard priority control function.
2. Description of the Related Art
A first conventional example of a hitless switching system is described in, for example, Japanese Laid Open Patent Application (JP-A-Heisei 9-83529). In this reference, hitless switching is realized by adjusting cell flows on 2-system transmission paths with redundant structure in phase. In an ATM cell flow control apparatus, a cell phase control is performed without influence of a policing function, even if the policing function is added to perform a discard control of any violation cell in the cell flow on each of 2-system transmission paths. In this method, a delay adjustment is performed to reception signals on 2-system transmission paths, which signals are shifted in phase due to the influence of the length difference between the duplicated transmission paths. Thus, the phases of the duplicated reception signals are matched to each other. In this way, the hitless switching is realized. A phase comparing circuit is provided at the front stage of the policing circuit, such that it is possible to avoid that a phase comparing operation is not correctly performed due to the influence of cell discarding by the policing circuit.
As a second conventional example, a hitless switching system is proposed in Japanese Laid Open Patent Application (JP-A-Heisei 8-186575), in which hitless switching is realized on the duplicated transmission paths. In the hitless switching system, like the technique which is described in the above Japanese Laid Open Patent Application (JP-A-Heisei 9-83529), the delay adjustment is performed to the reception signals of 2 systems in which phases are shifted. Thus, the duplicated reception signals are matched to each other in phase, so that the hitless switching is realized. Also, a phase comparison is performed based on the reception time of a monitoring cell which has been inserted by a transmission apparatus on the upper stream side on the transmission path.
As a third conventional example, an ATM switch is proposed in Japanese Laid Open Patent Application (JP-A-Heisei 8-139726), in which a buffer control of a hot standby system switch section is performed based on the number of cells remaining in two switch buffers. Thus, in the ATM switching system, the hitless switching is realized with a circuit of simple structure. FIGS. 1 and 2 show the structure of the first and second conventional examples of the hitless switching system.
As shown in FIG. 1, the conventional ATM switching system has a T cell inserting circuit 411, a branching circuit 412, a currently acting system switch 420, a standby system switch 430 and a selecting circuit 441. The currently acting system switch section 420 is composed of a buffer 421, a T cell detecting circuit 422 and a resident cell count detecting circuit 423. The standby system switch section 430 is composed of a buffer 431, a T cell detecting circuit 432, a resident cell count detecting circuit 433, a difference calculating circuit 434 and a read control circuit 435.
Also, the structure which is shown in FIG. 2 is composed of a threshold value comparing circuit 536 in the standby system switch 530 in addition to the structure of FIG. 1.
The ATM switching system which is proposed in the above Japanese Laid Open Patent Application (JP-A-Heisei 8-139726) shows a technique of realizing the hitless switching in the duplicated ATM switches in the apparatus. The number of cells stored in the currently acting system switch section and the number of cells stored in the standby system switch section are compared. When the number of cells stored in the currently acting system switch is larger, a cell reading operation from the standby system switch section is stopped for the difference between the number of cells stored in the currently acting system switch and the number of cells stored in the standby system switch. On the contrary, when the number of cells stored in the currently acting system switch is smaller, the reading operation address of the standby system switch section is proceeded for the difference. As a result, the number of cells stored in the standby system switch section is made to match to the number of cells stored in the currently acting system switch section. Thus, the hitless switching can be realized.
However, there is a problem in that both of the ATM cell flow control system mentioned in the above Japanese Laid Open Patent Application (JP-A-Heisei 9-83529) and the switching system mentioned in the above Japanese Laid Open Patent Application (JP-A-Heisei 8-186575) cannot be applied to the hitless switching of the ATM apparatus.
This is because both of the above conventional examples relate to the technique of realizing the hitless switching on the duplicated transmission paths. Therefore, the technique cannot be applied to the hitless switching in the switch sections of the ATM apparatus.
Also, the ATM switching system mentioned in the above Japanese Laid Open Patent Application (JP-A-Heisei 8-139726) might be applied to the hitless switching of the ATM switch. However, when the conventional ATM switching system is applied to the ATM switch having a discard priority control function, there is another problem in that the hitless switching cannot be performed.
This is because when the number of cells stored in one of the currently acting system switch section and the standby system switch section becomes larger than a threshold value of a low discard priority class while a process is performed to match the numbers of cells stored in both switch sections to each other, an input cell of the low discard priority class is discarded in one of the currently acting system switch section and the standby system switch section and stored in the other. Therefore, when the matching process is ended, the number of low discard priority class cells of the one switch section is different from that of the other switch section. In the structure shown in FIG. 2, the circuit for comparing threshold values is provided. However, the threshold value used in this circuit is not for the discard priority control. It is used for the determination of whether or not the cell storage states are matched.
In addition, a hitless switching system is described in Japanese Laid Open Patent Application (JP-A-Heisei 4-369140). In this reference, transmission path switching means of a transmission unit transmits an information sequence on a currently acting transmission path and a standby transmission path. Transmission path switching means of a reception unit is composed of delay inserting and removing means, delay control means and switching means. The delay inserting and removing means performs insertion or removal of a delay in units of cell lengths for a predetermined time period to the information sequence received from each transmission path. The delay control means controls the delay inserting and removing means such that the delay amounts of the information sequences are same. The switching means switches the output from the delay inserting and removing means of the currently acting system to the delay inserting and removing means of the standby system at the timing point when the delay amounts of the information sequences are same.
Also, an apparatus for matching byte phases of a transmission data in a currently acting system and standby system in an ATM communication system is described in Japanese Laid Open Patent Application (JP-A-Heisei 7-74756). In this reference, a cell head position of a readout data of a format conversion buffer 1A of the currently acting system A from an overhead is detected by a cell position byte counting circuit 3A and a cell position byte count corresponding to the detected byte count is notified to the standby system B. When the system is switched to the standby system B, a cell pulse generating circuit 5B of the standby system B determines a cell pulse generating timing of a cell pulse generating circuit 2B in accordance with the notified cell position byte count and controls a read operation from the buffer 1B. Thus, the hitless switching is made possible.
Also, a hitless switching apparatus is described in Japanese Laid Open Patent Application (JP-A-Heisei 8-23334). In this reference, an empty cell of an input signal is detected by an empty cell detecting sections 104 and 105. A portion of the input signal other than the detected empty cell is stored in memories 108 and 120. The signal of a currently acting system is sequentially read out and outputted via a selector 122. At this time, an empty cell is inserted on the same position as that of the detected empty cell by an empty cell detecting section 115. In this case, a cell is latched in either of the cell buffer 112 and the cell buffer 121 and is compared with a cell read out form the other by a comparing section to determine whether or not both of the cells are coincident with each other. When the coincidence is detected, the difference between the memories 108 and 120 in cell storage amount is determined so as to set an empty cell counter so that the empty cell is inserted by the empty cell inserting section 115. Thus, the hitless switching is realized.
Also, a hitless switching apparatus is described in Japanese Laid Open Patent Application (JP-A-Heisei 8-251184). In this reference, HEC error detecting sections 14-1 and 14-2 are connected to a currently acting system transmission path and a standby system transmission path, respectively, and outputs of them is connected to a selector 12. When a HEC error is detected by the HEC error detecting sections 14-1 of the currently acting system, a switching control section 13 generates a switching instruction such that the selector 12 selects the output of the HEC error detecting sections 14-2 of the standby system.
Also, a virtual path switching apparatus is described in Japanese Laid Open Patent Application (JP-A-Heisei 8-237253). In this reference, a sequence number and an identification code indicative of whether or not switching is necessary are given is allocated to a switching control OAM cell. The switching control OAM cell is intermittently transmitted on duplicate virtual paths (VPs: VP10T and VP11T) from a switching control OAM cell generating and inserting circuit 1-1. The delay difference between the virtual paths and the loss of the switching control OAM cell are detected by a VP reception node 2 such that switching between the VPs is performed in the state in which synchronization is established.
The present invention is accomplished in the viewpoint of the above problems. Therefore, an object of the present invention is to provide a hitless switching system of an ATM apparatus which has a discard priority control function.
In order to achieve an aspect of the present invention, a hitless switching system in an asynchronous transfer mode (ATM) apparatus, includes a first system switch section set as a currently acting system switch section and a second system switch section set as a hot standby system switch section. Each of the first and second system switch sections is switchable between the currently acting system switch section and the hot standby system switch section.
The first system switch section has a first cell buffer, and sequentially stores a sequence of cells in the first cell buffer to sequentially output the stored cells from the first cell buffer while performing a discard priority control to the sequence of cells. Also, the first system switch section stops the discard priority control when a switching control cell is detected in the sequence of cells. The second system switch section has a second cell buffer, and sequentially stores the input cells in the second cell buffer to sequentially output the stored cells from the second cell buffer while performing the discard priority control to the sequence of cells. When the switching control cell is detected in the input cell, the second system switch section stops the discard priority control and discards the stored cells from the second cell buffer together with the switching control cell.
The discard priority control may have a plurality of levels. Each of the plurality of levels is associated with a storage capacity of the first or second cell. The first cell buffer is equal to the second cell buffer in storage capacity. The switching control cell is inserted in the sequence of cells.
In the above, the first system switch section sequentially outputs stored cells from the first cell buffer, sets a first mode of the first system switch section when the switching control cell is detected as one of the sequence of cells, stores the sequence of cells in the first cell buffer in the first mode while stopping the discard priority control to the sequence of cells, and selectively stores a sequence of cells in the first cell buffer in a state in which the first mode is not set while performing the discard priority control to the sequence of cells. Also, the second system switch section does not output stored cells from the second cell buffer in a second mode and sequentially outputs the stored cells from the second cell buffer when the second mode is not set, sets the second mode when the switching control cell is detected in the sequence of cells to the second cell buffer, discards the stored cells from the second cell buffer together with the switching control cell when the second mode is set, stores the sequence of cells in the second cell buffer in the second mode while stopping the discard priority control to the sequence of cells, and selectively stores the sequence of cells in the second cell buffer in a state in which the second mode is not set while performing the discard priority control to the sequence of cells.
The hitless switching system may further include an input interface section which includes a switching control inserting section for generating the switching control cell in response to an insert instruction and inserting the switching control cell in a sequence of cells, and a branching circuit for supplying the sequence of cells to the first system switch section and the second system switch section.
In this case, the first system switch section may include the first cell buffer, a first detecting section for detecting the switching control cell in the sequence of cells to the first cell buffer to generate a first detection signal, and a second detecting section for detecting the switching control cell in the sequence of cells from the first cell buffer to generate a second detection signal, and a first control section. The first control section sets the first mode in response to the first detection signal, cancels the first mode in response to the second detection signal, stores the sequence of cells in the first cell buffer in the first mode while stopping the discard priority control, selectively stores the sequence of cells in the first cell buffer in a state in which the first mode is not set while performing the discard priority control to the sequence of cells, and sequentially outputs stored cells from the first cell buffer. Also, the second system switch section includes the second cell buffer, a third detecting section for detecting the switching control cell in the sequence of cells to the second cell buffer to generate a third detection signal, and a second control section. The second control section sets the second mode in response to the third detection signal, discards the stored cells from the second cell buffer together with the switching control cell when the second mode is set, stores the sequence of cells in the second cell buffer in the second mode while stopping the discard priority control, selectively stores the sequence of cells in the second cell buffer in a state in which the second mode is not set while performing the discard priority control to the sequence of cells, and sequentially outputs stored cells in the second cell buffer in the state in which the second mode is not set. In this case, the hitless switching system may further include an output interface section which includes a selecting circuit for selecting one of the cells outputted from the first system switch section and the cells outputted from the second system switch section in response to a selection control signal.
Instead, the first system switch section includes the first cell buffer, a first detecting section for detecting the switching control cell in the sequence of cells to the first cell buffer to generate a first detection signal, and a first control section. The first control section sets the first mode in response to the first detection signal, cancels the first mode in response to a second detection signal, stores the sequence of cells in the first cell buffer in the first mode while stopping the discard priority control, selectively stores the sequence of cells in the first cell buffer in a state in which the first mode is not set while performing the discard priority control to the sequence of cells, and sequentially outputs stored cells from the first cell buffer. The second system switch section includes the second cell buffer, a third detecting section for detecting the switching control cell in the sequence of cells to the second cell buffer to generate a third detection signal, and a second control section. The second control section sets the second mode in response to the third detection signal, cancels the second mode in response to the second detection signal, discards the stored cells in the second cell buffer together with the switching control cell when the second mode is set, stores the sequence of cells in the second cell buffer in the second mode while stopping the discard priority control, selectively stores the sequence of cells in the second cell buffer in a state in which the second mode is not set while performing the discard priority control to the sequence of cells, and sequentially outputs stored cells from the second cell buffer in a state in which the second mode is not set.
In this case, the hitless switching system may further include an output interface section which includes a selecting circuit for selecting one of the cells outputted from the first system switch section and the cells outputted from the second system switch section in response to a selection control signal, and a second detecting section for detecting the switching control cell in the sequence of cells from the first cell buffer to generate the second detection signal.
The hitless switching system may include an input interface section which includes a branching circuit for supplying the sequence of cells to the first system switch section and the second system switch section.
In this case, the first system switch section includes the first cell buffer, a switching control inserting section for generating the switching control cell in response to an insert instruction and inserting the switching control cell in the sequence of cells including the first and second cells, a first detecting section for detecting the switching control cell in the sequence of cells to the first cell buffer to generate the first detection signal, a second detecting section for detecting the switching control cell in the sequence of cells from the first cell buffer to generate the second detection signal, and a first control section. The first control section sets the first mode in response to the first detection signal, cancels the first mode in response to the second detection signal, stores the sequence of cells in the first cell buffer in the first mode while stopping the discard priority control, selectively stores the sequence of cells in the first cell buffer in a state in which the first mode is not set while performing the discard priority control to the sequence of cells, and sequentially outputs stored cells from the first cell buffer. Also, the second system switch section includes the second cell buffer, a switching control inserting section for generating the switching control cell in response to an insert instruction and inserting the switching control cell in the sequence of cells including the first and second cells, a third detecting section for detecting the switching control cell in the sequence of cells to the second cell buffer to generate the third detection signal, and a second control section. The second control section sets the second mode in response to the third detection signal, cancels the second mode in response to the second detection signal, discards the stored cells from the second cell buffer together with the switching control cell when the second mode is set, stores the sequence of cells in the second cell buffer in the second mode while stopping the discard priority control, selectively stores the sequence of cells in the second cell buffer in a state in which the second mode is not set while performing the discard priority control to the sequence of cells, sequentially outputs stored cells from the second cell buffer in the state in which the second mode is not set.
In this case, the hitless switching system may further include an output interface section which includes a selecting circuit for selecting one of the cells outputted from the first system switch section and the cells outputted from the second system switch section in response to a selection control signal.
Moreover, the hitless switching system may include a plurality of sets of the first system switch section and the second system switch section, a plurality of input interface sections, each of which supplies a sequence of cells, and a cell interleaving circuit for supplying each of the plurality of sequences of cells to a corresponding one of the plurality of sets of the first system switch section and the second system switch section.
In order to achieve another aspect of the present invention, a hitless switching method in an asynchronous transfer mode (ATM) apparatus, includes the steps of:
sequentially outputting stored cells in a first cell buffer of a first system switch section;
setting a first mode when a switching control cell is detected as an input cell to the first cell buffer;
storing a sequence of cells in the first cell buffer in the first mode while stopping a discard priority control;
selectively storing the sequence of cells in the first cell buffer in a state in which the first mode is not set while performing the discard priority control to the sequence of cells;
setting a second mode when the switching control cell is detected as an input cell to a second cell buffer;
sequentially outputting stored cells from the second cell buffer in a state in which the second mode is not set;
discarding the stored cells from the second cell buffer when the second mode is set;
storing the sequence of cells in the second cell buffer in the second mode while stopping the discard priority control to the sequence of cells;
selectively storing the sequence of cells from the second cell buffer in the state in which the second mode is not set while performing the discard priority control to the sequence of cells; and
selecting one of the cells sequentially outputted from the first cell buffer and the cells sequentially outputted from the second cell buffer.